How to calculate Cp, Cpk and Ppk
The Design limits include Upper Specification Limit USL and
Lower Specification Limit LSL. The measurements include sample mean
m', lot mean m, estimated standard deviation s', and
standard deviation s.
Calculate Cp which is a process index that relates the specification
range to process variation.
Cp = (USL-LSL)/6s'
Cpk is a process index that relates the process mean to the nominal
value of the two sided specification. First determine the difference
between the process mean and the specification limits.
XUSL = (USL-m')
XLSL = (LSL-m')
Select the minimum of the two values.
XMIN = min[XUSL, - XLSL]
Cpk is found by the following.
Cpk = XMIN/3s'
Relation between Cp and Cpk
Cpk = Cp(1-K)
K is found with Target value T, which is the center of the
specification range, and Specification width W, which is the
K = (m' - T)/(W/2)
T = (USL – LSL)/2
W = USL-LSL
Ppk is the same as Cpk, however replace m' and s' with m
and s. Its a difference of sample verse lot.
Ideal Test Limits
You might think that big Cpk numbers mean good test limits, but
that's wrong. Cpk= 1.33 (4 StdDev) is about ideal, a little
larger is often needed in electronics to allow component variably
that can't be controlled. You should consider reducing the test
limits if Cpk is 1.67 (5 StdDev) or larger. Some Quality people
would say I was nut's for saying this but the job of test is to find
things that are bad, or put another way unlikely to be good. If the
test is passing some units outside 4 StdDev they probability have a
What are production Outliers? This is a unit that falls in the
gray area of being statistically unlikely but within the design
limits. Outliers are detected with probability.
Some time back I design an automatic test system that tested and
passed over 12,000 power processing devices, it passed 63 units
outside four standard deviations, i.e. Outliers. Assuming a normal
distribution only 0.0063 percent should fail, less than one part
Statistically. I am aware of reliability problems inherent in
outliers. I have performed analysis on some of these units and saw
things like increased resistance due to an open in one of the
parallel windings, partial solder flow, wrong value parts. A well
tested product looks at characteristics that maximize the use of
statistics. One of the best examples I know is using bias levels in
circuits that come into play only under cretin conditions like light
load, thermal shutdown, current limit, input lockout and output
lockout. These bias level test reveal circuit failures as outliers,
without adding complex test methods.
+/- 1 standard deviation 68.27%
+/- 2 standard deviation 95.45%
+/- 3 standard deviation 99.73%
+/- 4 standard deviation 99.9936%
+/- 5 standard deviation 99.999943%
Statistical Quality Design and Control 1992 Prentice-Hall, Inc.
Process Measurement By Hawthorne SMT February 1997
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